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Univ. of Minnesota, Minneapolis, MN

FPGA Exercises in the Advanced Lab

Dates:   May 18, 2022  to  May 20, 2022

Number of setups available: 8

Maximum number of participants: 8


In this workshop you will work with FPGAs (Field Programmable Gate-Arrays.) Unlike the older, traditional application specific standard products (ASSPs), such as the 4000 or 7400 series chips, FPGAs contain 100k or more logic gates which can be operated reliably in the MHz to GHz range. These properties make FPGAs ideally suited to be used in an advanced lab course teaching digital logic or to have them directly incorporated into lab projects.

You will interface the Digilent’s BASYS3 FPGA hardware boards and learn how to implement combinational and sequential digital logic using a hardware descriptive language, such as Verilog and Xilinx’s Vivado compiler.  You will build an interactive 8 bit adder and subtractor.  The pulse width modulation (PWM) technique will be applied to build a digital-to-analog converter to play music.  An 8-digit period and frequency counter will be implemented with a state machine and an IP core based microprocessor will be embedded in the FPGA to communicate the results to a PC over an USB port.

Time permitting, we’ll do additional exercises such as using an IP core to create a sinusoidal frequency synthesizer, a successive-approximation analog-to-digital converter or build a coincidence counter driven by a couple of GM tubes; use the digital clock manager to control the system clock and work with other educational hardware options, such as National Instruments CompactRIO.  All equipment and software will be provided.

Experiment Costs: The actual FPGA boards cost $89 with academic discount. Additional plug-in boards used during the workshop add another $100 to $150. The compiler software is free. You will also need a computer and an oscilloscope.

Host and Mentors:

Kurt Wick (B.S. 1986, M.A. 1989, University of Minnesota), together with faculty, has been developing and teaching the advanced lab at the University of Minnesota for the last 23 years. He always has been interested in the electronics and computer interfacing aspect of the course. About 10 years ago FPGAs were included in the lab course. The reasoning was that, first, the old 74 series chip were rarely being used anymore in the real world; second, just when the digital circuits began to get interesting for students, i.e., as the size and speed of the design increased, the circuits became extremely tedious and difficult to construct on a bread board. What he immediately liked about the FPGAs was that it freed him from these two constraints while still being able to teach the fundamental aspects of digital logic. Students now can expand their knowledge and apply it to more challenging and rewarding designs that are also in sync with current technologies.

Kurt Wick, Education Program Specialist II, University of Minnesota, School of Physics and Astronomy, 116 Church St. SE, Minneapolis, MN 55455 Email: Telephone: 612-624-2831

Kevin Booth (B.S. 2015, currently finishing his M.S. at the University of Minnesota) has been working alongside Kurt Wick in the Advanced Lab at the University of Minnesota for the last 3 years. While taking the advanced lab courses as an undergrad, he became fascinated by the experimental tools available in the lab and he is now developing new ways to expose students to these tools. He has worked with Kurt in implementing new experiments using FPGAs, providing students with a better understanding of the power and utility of this digital tool.

Kevin Booth, Research Professional III, University of Minnesota, School of Physics and Astronomy, 116 Church St. SE, Minneapolis, MN 55455 Email: Telephone: 612-624-2831

Please note that the Jonathan F. Reichert Foundation has established a grant program to help purchase apparatus used in Laboratory Immersions. Limitations and exclusions apply, but generally speaking the Foundation may support up to 40% of the cost of the required equipment. FPGAs are likely excluded; however, apparatus controlled by an FPGA might be supported.

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